Physical Design Engineer

Physical Design Engineer

Experience Level 3–8 years]

Industry: Semiconductors / VLSI

Job Description:

We are looking for a skilled and motivated Physical Design Engineer to join our growing team. You will be responsible for end-to-end physical implementation of complex digital blocks or SoCs, ensuring timing, power, and area goals are met. This role involves close collaboration with RTL design, DFT, STA, and verification teams to drive high-quality GDSII deliveries.

Key Responsibilities:

• Own physical implementation from RTL/netlist to GDSII
• Perform floorplanning, power planning, placement, CTS, and routing
• Conduct timing closure using static timing analysis (STA) tools
• Run physical verification: DRC, LVS, Antenna, and EM/IR analysis
• Drive design optimization to meet PPA (power, performance, area) targets
• Handle ECOs (Engineering Change Orders) and support tape-out activities
• Work with low-power design techniques (UPF/CPF)
• Collaborate across functions to resolve integration issues and improve flow efficiency

Requirements:

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field
• [3+] years of experience in Physical Design at block or full-chip level
• Strong experience with tools like Synopsys ICC2, Cadence Innovus, Primetime
• Solid understanding of STA, clock tree synthesis, and signal integrity
• Familiar with DRC/LVS sign-off and methodologies (Calibre/ICV)
• Good scripting skills in TCL, Perl, or Python for automation
• Exposure to advanced technology nodes (e.g., 7nm, 5nm, 3nm) is a plus
• Excellent communication and problem-solving skills

Preferred Qualifications:

• Experience with hierarchical design methodology
• Background in power-aware design and sign-off
• Familiarity with industry-standard EDA flows and methodologies

Why Join Us:

• Opportunity to work on cutting-edge technology nodes
• Collaborative and innovative team culture
• Competitive compensation and growth potential