Physical Design Engineer

As a Physical Design Engineer, you will be responsible for transforming RTL/logic designs into manufacturable integrated circuits (ICs) by performing physical implementation, optimization, and verification. You will work with advanced EDA tools to achieve performance, power, and area (PPA) targets while ensuring design integrity and manufacturability.

Key Responsibilities:

1. Physical Implementation & Optimization

• Perform floorplanning to define macro placement, power grid, and hierarchical partitioning for optimal chip utilization.
• Execute cell placement using industry-standard P&R tools (e.g., Cadence Innovus, Synopsys ICC2) to minimize congestion and wirelength.
• Design and optimize clock tree synthesis (CTS) for low skew and power efficiency.
• Conduct global and detailed routing while addressing signal integrity, EM/IR, and timing constraints.

1. Timing & Power Closure

• Achieve timing closure through STA (Static Timing Analysis) and optimization techniques (e.g., buffering, sizing, VT-swapping).
• Implement low-power design techniques, including clock gating, power gating, and multi-Vt optimization.

1. Verification & Sign-off

• Perform physical verification (DRC, LVS, ERC) using Calibre or Pegasus.
• Validate power integrity (EM/IR drop analysis) and signal integrity (crosstalk mitigation).
• Generate and review sign-off reports for tape-out readiness.

1. Collaboration & Methodology

• Work closely with RTL design, DFT, and CAD teams to ensure seamless integration.
• Develop and enhance physical design methodologies (e.g., automation scripts in Tcl/Python).
• Support ECO implementation for functional and timing fixes.

1. Documentation & Process Improvement

• Maintain detailed design documentation (constraints, reports, runbooks).
• Contribute to flow automation and tool efficiency improvements.

Required Skills & Tools:

• EDA Tools: Synopsys Fusion Compiler, Cadence Innovus, Primetime, Tempus, Voltus
• Methodologies: Hierarchical design, multi-corner/multi-mode (MCMM) analysis
• Scripting: Tcl, Python, Perl for automation & flow enhancement
• Verification: DRC/LVS (Calibre), STA (PrimeTime), EM/IR (Redhawk/Voltus)

We regret that only shortlisted candidates will be notified

Email resume to tiffany@peopleprofilers.com

People Profilers Pte Ltd, 20 Cecil Street, #08-09, PLUS Building, Singapore 049705.

Tel: 6950 9722

Posting Personnel: Tiffany Ong Meng Yen